| By James Colgan |
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| March 5, 2013 06:39 PM EST |
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423 |
Came across a great panel discussion from DAC 2012 that’s really worth a watch. Hosted by David Murray of Duolog, the panel includes Mike Stellfox of Cadence, Harry Foster of Mentor Graphics, Paul Martin of ARM, and Warren Stapleton of AMD.
The main thrust of the conversation is centered on SoC integration efficiency and how SoC verification has become a major component or driver of it.
Take a look here:
http://www.youtube.com/watch?v=UO18Gkqo8vU
Closely related to this topic are the tools that Duolog provide to increase SoC integration efficiency. You can try these tools out for free on the cloud here:
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Duolog’s Weaver tool has a unique rules-based integration methodology that offers an intuitive, highly automated, scalable solution for IP integration and system assembly. |
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Duolog’s Bitwise tool manages HW/SW register, memory-map and interface definitions for IPs, subsystems or SoCs. Bitwise automatically generates specifications for register and memory-map information. |
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Duolog’s Spinner tool specifies the complete I/O layer, auto-generates multiple design views and enables seamless integration of the I/O fabric with the rest of the system. |
James Colgan is the Founder and CEO of Xuropa, a unique cloud-based Sales & Marketing Platform for packaged software vendors for the demo and retail of their products via the cloud. Built upon a unique lead nurturing and analytics engine, Xuropa enables software vendors to conveniently deliver their products on the cloud and drive the resultant sales pipeline to increase revenues and profits.
Built upon nearly 20 years of high-tech experience, James has been pushing the envelope of cloud computing, focused on the intersection between the cloud, Customer Relationship Management (CRM), and Social Media Marketing, particularly as it relates to traditional installed software.
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